integrated device technology, inc. description: the fct163374/a/c 16-bit edge-triggered d-type regis- ters are built using advanced dual metal cmos technology. these high-speed, low-power registers are ideal for use as buffer registers for data synchronization and storage. the output enable (x oe ) and clock (xclk) controls are organized to operate each device as two 8-bit registers or one 16-bit register with common clock. flow-through organization of signal pins facilitates ease of layout. all inputs are designed with hysteresis for improved noise margin. the inputs of fct163374/a/c can be driven from either 3.3v or 5v devices. this feature allows the use of these devices as translators in a mixed 3.3v/5v supply system. 3.3v cmos 16-bit register (3-state) idt74fct163374/a/c the idt logo is a registered trademark of integrated device technology, inc. commercial temperature range august 1996 1 features: ? 0.5 micron cmos technology ? typical t sk (o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ? packages include 25 mil pitch ssop, 19.6 mil pitch tssop and 15.7 mil pitch tvsop ? extended commercial range of -40 c to +85 c ?v cc = 3.3v 0.3v, normal range or v cc = 2.7 to 3.6v, extended range ? cmos power levels (0.4 m w typ. static) ? rail-to-rail output swing for increased noise margin ? low ground bounce (0.3v typ.) ? inputs (except i/o) can be driven by 3.3v or 5v components 1 o 1 1 oe 1 clk 1 d 1 2775 drw 01 to 7 other channels c d 2 o 1 2 oe 2 clk 2 d 1 to 7 other channels c d 2775 drw 02 functional block diagram 8.5 1996 integrated device technology, inc. dsc-4637/5
8.5 2 idt74fct163374/a/c 3.3v 16-bit register (3-state) commercial temperature range pin configurations 1 o 1 gnd 1 o 3 v cc 1 oe gnd 2 o 2 gnd v cc gnd 1 o 2 1 o 4 1 o 5 1 o 6 1 o 7 1 o 8 2 o 1 2 o 3 2 o 4 2 o 5 2 o 7 2 o 8 2 o 6 2 oe 1 clk 1 d 1 1 d 2 gnd 1 d 3 1 d 4 v cc 1 d 5 1 d 6 1 d 7 1 d 8 2 d 1 2 d 2 2 d 3 2 d 4 v cc 2 d 5 2 d 7 2 d 8 2 d 6 2 clk gnd gnd gnd 2775 drw 03 39 29 30 31 32 33 34 35 36 37 38 25 26 27 28 48 47 41 42 43 44 45 46 40 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 21 22 23 24 ssop/ tssop/tvsop top view so48-1 so48-2 so48-3 pin description 2775 tbl 01 pin names description xdx data inputs xclk clock inputs xox 3-state outputs. x oe 3-state output enable input (active low) absolute maximum ratings (1) symbol description max. unit v term (2) terminal voltage with respect to gnd C0.5 to +4.6 v v term (3) terminal voltage with respect to gnd C0.5 to +7.0 v v term (4) terminal voltage with respect to gnd C0.5 to v cc + 0.5 v t stg storage temperature C65 to +150 c i out dc output current C60 to +60 ma notes: 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect reliability. 2. vcc terminals. 3. input terminals. 4. output and i/o terminals. 2775 lnk 03 function table (1) note: 2775 tbl 02 1. h = high voltage level l = low voltage level x = dont care z = high impedance - = low-to-high transition inputs outputs function xdx xclk x oe oe xox hi-z x l h z xhhz load l - ll register h - lh l - hz h - hz capacitance (t a = +25 c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 3.5 6.0 pf c out output capacitance v out = 0v 3.5 8.0 pf note: 1. this parameter is measured at characterization but not tested. 2775 lnk 04
8.5 3 idt74fct163374/a/c 3.3v 16-bit register (3-state) commercial temperature range dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = C40 c to +85 c, v cc = 2.7v to 3.6v 2775 lnk 05 symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level (input pins) guaranteed logic high level 2.0 5.5 v input high level (i/o pins) 2.0 v cc +0.5 v il input low level guaranteed logic low level C0.5 0.8 v (input and i/o pins) i i h input high current (input pins) v cc = max. v i = 5.5v 1 m a input high current (i/o pins) v i = v cc 1 i i l input low current (input pins) v i = gnd 1 input low current (i/o pins) v i = gnd 1 i ozh high impedance output current v cc = max. v o = v cc 1 m a i ozl (3-state output pins) v o = gnd 1 v ik clamp diode voltage v cc = min., i in = C18ma C 0.7 C 1.2 v i odh output high current v cc = 3.3v, v in = v ih or v il, v o = 1.5v (3) C36 C60 C110 ma i odl output low current v cc = 3.3v, v in = v ih or v il, v o = 1.5v (3) 50 90 200 ma v oh output high voltage v cc = min. i oh = C0.1ma v cc C 0.2 v v in = v ih or v il i oh = C3ma 2.4 3.0 v cc = 3.0v v in = v ih or v il i oh = C8ma 2.4 (5) 3.0 v ol output low voltage v cc = min. i ol = 0.1ma 0.2 v v in = v ih or v il i ol = 16ma 0.2 0.4 i ol = 24ma 0.3 0.55 v cc = 3.0v v in = v ih or v il i ol = 24ma 0.3 0.50 i os short circuit current (4) v cc = max., v o = gnd (3) C60 C 135 C240 ma v h input hysteresis 150 mv i ccl i cch quiescent power supply current v cc = max., v in = gnd or v cc 0.1 10 m a i ccz notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 3.3v, +25 c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. this parameter is guaranteed but not tested. 5. v oh = v cc C0.6v at rated current.
8.5 4 idt74fct163374/a/c 3.3v 16-bit register (3-state) commercial temperature range power supply characteristics notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 3.3v, +25 c ambient. 3. per ttl driven input; all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp n cp /2 + fini) i cc = quiescent current (i ccl, i cch and i ccz ) d i cc = power supply current for a ttl high input d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp f i = input frequency n i = number of inputs at fi 2775 tbl 07 symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply current v cc = max. v in = v cc C 0.6v (3) 2.0 30 m a i ccd dynamic power supply current (4) v cc = max. outputs open x oe = gnd 50% duty cycle one input toggling v in = v cc v in = gnd 5075 m a/ mhz i c total power supply current (6) v cc = max. outputs open f cp = 10mhz 50% duty cycle v in = v cc v in = gnd 0.5 0.8 ma x oe = gnd fi = 5mhz 50% duty cycle one bit toggling v in = v cc C0.6v v in = gnd 0.5 0.8 v cc = max. outputs open f cp = 10mhz 50% duty cycle v in = v cc v in = gnd 2.5 3.8 (5) x oe = gnd fi = 2.5mhz 50% duty cycle sixteen bits toggling v in = v cc C0.6v v in = gnd 2.5 4.0 (5)
8.5 5 idt74fct163374/a/c 3.3v 16-bit register (3-state) commercial temperature range switching characteristics over operating range (4) fct163374 fct163374a fct163374c symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. unit t plh t phl propagation delay xclk to xox c l = 50pf r l = 500 w 2.0 10.0 2.0 6.5 2.0 5.2 ns t pzh t pzl output enable time 1.5 12.5 1.5 6.5 1.5 5.5 ns t phz t plz output disable time 1.5 8.0 1.5 5.5 1.5 5.0 ns t su set-up time high or low, xdx to xclk 2.0 2.0 2.0 ns t h hold time high or low, xdx to xclk 1.5 1.5 1.5 ns t w xclk pulse width high or low 7.0 5.0 5.0 ns t sk (o) output skew (3) 0.5 0.5 0.5 ns notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design. 4. propagation delay and enable/disable times are with v cc = 3.3v 0.3v, normal range. for v cc = 2.7v to 3.6v, extended range, all propagation delays and enable/disable times should be degraded by 20%. 2775 tbl 08
8.5 6 idt74fct163374/a/c 3.3v 16-bit register (3-state) commercial temperature range definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3v 0v output normally low output normally high switch 6v switch gnd v ol 0.3v 0.3v t plz t pzl t pzh t phz 3v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w gnd 6v ? open test circuits and waveforms test circuits for all outputs enable and disable times propagation delay set-up, hold and release times pulse width switch position 2775 drw 09 2775 drw 07 2775 drw 05 2775 drw 06 2775 drw 08 test switch open drain disable low enable low 6v disable high enable high gnd all other tests open 2775 lnk 09 notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. 3. if v cc is below 3v, input voltage swings should be adjusted not to exceed v cc .
8.5 7 idt74fct163374/a/c 3.3v 16-bit register (3-state) commercial temperature range ordering information idt xx temp. range xxxx device type x package pv pa pf 374 374a 374c shrink small outline package (so48-1) thin shrink small outline package (so48-2) thin very small outline package (so48-3) non-inverting 16-bit register 74 C40 c to +85 c 2775 drw 10 fct 163 16-bit 3.3 volt x family
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